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| AD120 Preliminary Document Title 3-Level / 258 Outputs TFT LCD Gate Driver Revision History Rev. No. 0.0 3-Level / 258 Outputs TFT LCD Gate Driver History Initial issue Issue Date August 10, 2001 Remark Preliminary Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer. PRELIMINARY (August, 2001, Version 0.0) AMIC Technology, Inc. AD120 Preliminary Features n n n n n TFT LCD gate driver 3-level / 258 outputs 40V max. for each output -15V min. for each output 2.7V~3.6V logic input/output level n Bi-directional data shift control n Output waveform control n TCP available 3-Level / 258 Outputs TFT LCD Gate Driver AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three-level output allows voltage correction for better switching noise rejection. It can be used for XGA / SXGA panels. Block Diagram ST1 ST2 ST1X Shift Register R/L CP ST2X ......... XOFF XON OGW Decoder ......... VH VOFF VL VDD VSS Output ......... OUT0 OUT1 OUT2 ......... OUT255 OUT256 OUT257 PRELIMINARY (August, 2001, Version 0.0) 1 AMIC Technology, Inc AD120 TCP Pinout 18 19 20 21 22 OUT0 OUT1 OUT2 OUT3 OUT4 VL VOFF VH ST1 ST2 VSS CP VDD XOFF XON R/L OGW ST2X ST1X VH VOFF VL 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AD120 271 272 273 274 275 PRELIMINARY (August, 2001, Version 0.0) 2 AMIC Technology, Inc ....................................................................... OUT253 OUT254 OUT255 OUT256 OUT257 ...................................................................... AD120 Input/Output Pin Function Pin No. 11 7 Symbol CP I/O I I Description Clock pulse Right / left direction control for shift register When R /L is LOW, data are shifted to the right, or ST1 / ST2 .... output257. R /L output0 output1 When R /L is HIGH, data are shifted to the left, or ST1X / ST2X output256 .... output0. 8 output257 XON XOFF OGW ST1, ST2, ST1X, ST2X I XON to force all the outputs to VH voltage. It is not synchronous to CP. XOFF to force all the outputs to VOFF voltage. It is not synchronous to CP. Output Gate pulse Width to select output_waveform format. When R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined as outputs . The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses. When R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined as outputs. The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses. Output drivers These outputs are synchronized to CP pulses. The output format and voltage level are controlled by OGW, XON , XOFF , ST1 / ST2, ST1X / ST2X and R /L correspondingly as shown in the diagram. Reference voltage Supply voltage for logic operation VDD and VSS are voltage levels of input / output logic signals High voltage for output drivers Low voltage for output drivers OFF voltage for output drivers 9 I 6 4,5, 13,14 I I/O 18 - 275 OUT0~ OUT257 O 12 10 3, 15 1, 17 2, 16 VSS VDD VH VL VOFF PWR PWR PWR PWR PWR PRELIMINARY (August, 2001, Version 0.0) 3 AMIC Technology, Inc AD120 Description Operation Output signals OUT0~OUT257 are used for control of the TFT gates of the LCD panel. A bi-directional shift register is implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi-directional shift register and the direction of the register is controlled by R /L signal. When R /L is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. When R /L is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. 3-Level Output VH - VL = 40V(max.) VOFF - VL = 0~10V VH - VSS = 17~28V OUT VH Level VDD VSS VOFF VL PRELIMINARY (August, 2001, Version 0.0) 4 AMIC Technology, Inc AD120 Operation Diagram 1 (R /L = L, OGW = L) 1 CP VDD ST1 VSS VDD ST2 VSS VH OUT0 VOFF VL VH OUT1 VOFF VL VH VOFF VL VH OUT3 VOFF VL VH OUT256 VOFF VL VH OUT257 VOFF VL VDD ST1X VSS 2 3 256 257 VDD ST2X ~ ~ VSS ~ ~ ~ ~ ~ ~ ~ ~ OUT2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ PRELIMINARY (August, 2001, Version 0.0) 5 AMIC Technology, Inc AD120 Operation Diagram 2 (R /L = L, OGW = H) 1 CP 2 3 ST1 ST2 XOFF VDD VSS XON VDD VSS VH OUT0 VOFF VL VH OUT1 VOFF VL OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 PRELIMINARY (August, 2001, Version 0.0) 6 AMIC Technology, Inc AD120 Table 1. Function of XON and XOFF XON L H H XOFF X L H OUT0~OUT257 VH VOFF Table2 * The outputs are asynchronous to CP. Table 2. Control of OUT1~OUT256 ( XON = H, XOFF = H) (R /L = L) (R /L = H) ST1 ST1X L L H ST2 ST2X L H L X X X L H H H * The outputs are synchronous to CP. VH (CP = "L") VL (CP = "H") VOFF VL VL VH OGW OUT1~OUT256 Table 3. Control of OUT0 and OUT257 ( XON = H, XOFF = H) (R /L = L) (R /L = H) ST1 ST1X L L H H * The outputs are synchronous to CP. ST2 ST2X L H L H OUT0 OUT257 VOFF VL VL VL PRELIMINARY (August, 2001, Version 0.0) 7 AMIC Technology, Inc AD120 Absolute Maximum Ratings Over Operating Free-air Temperature Range Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage Storage Temperature Symbol VDD VH VL VOFF VH - VL VIN Tstg Ratings -0.3 ~ +7.0 -0.3 ~ 42.0 -20.0 ~ +0.3 VL-0.3 ~ VL+11.0 -0.3 ~ 42.0 -0.3 ~ VDD+0.3 -55 ~ 125 Unit V V V V V V C Power_on Sequence and Voltage Levels VH VDD Out0~Out257 VSS VOFF VL VDD Logic Signal VSS Operating Voltage Range Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Clock Frequency Operating Free-air Temperature Symbol VDD VH VL VOFF - VL VH - VL fCP Ta Min. 2.7 17 -15 0 22 -20 Typ. 3.3 Max. 3.6 28 -5 10.0 40 100 +75 Unit V V V V V KHz C PRELIMINARY (August, 2001, Version 0.0) 8 AMIC Technology, Inc AD120 DC Charactertics (VDD = 2.7~3.6V, Ta = -20~75C) Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Output Resistance (1) Output Resistance (2) Output Resistance (3) Input Current Operating Current (1) Operating Current (2) Notes: 1. VH = 25V, VOFF = 0V, VL = -10V 2. CP = 50KHz Symbol VIL VIH VOL VOH RL ROFF RH II IDD IH IOL = 40A IOH = 40A VOUT = VL + 0.5 VOUT = VOFF + 0.5 VOUT = VH - 0.5 VI = VDD / VSS -5.0 Condition Min. VSS 0.8 X VDD VSS VDD -0.4 Max. 0.2 X VDD VDD VSS + 0.4 VDD 1000 1000 1000 +5.0 1500 100 Unit V V V V U U U A A A Applicable Pin All input pins All input pins ST1, ST2, ST1X, ST2X OUT0~OUT257 OUT0~OUT257 OUT0~OUT257 All input pins VDD VH 1, 2 1, 2 1 1 1 Note AC Charactertics (VDD = 2.7~3.6V, Ta = -20~75C) Parameter Clock Frequency CP High Pulse Width CP Low Pulse Width Input Rise Time Input Fall Time Gate Off Time Data Setup Time Data Hold Time Delay Time 1 Delay Time 2 Delay Time 3 Delay Time 4 Delay Time 5 Symbol fCP tCPH tCPL tr tf tWOFF tSU thd tpd1 tpd2 tpd3 tpd4 tpd5 CL = 20pF CL = 300pF CL = 300pF CL = 300pF CL = 300pF 10% ~ 90% 90% ~ 10% 1 700 700 800 1000 1000 1000 1000 1 4 50 50 Condition Min. Max. 100 Unit KHz s s ns ns s ns ns ns ns ns ns ns PRELIMINARY (August, 2001, Version 0.0) 9 AMIC Technology, Inc AD120 Timing Waveform 1 tCPH 0.5 x V DD tCPL 0.5 x V DD 2 256 257 0.5 x V DD 0.5 x V DD 0.5 x V DD 0.5 x V DD CP tSU thd ST1, ST2 Input 0.5 x V DD ~ ~ tpd1 0.5 x V DD ~ ~ tpd1 50% 50% STX1, STX2 Output tpd2 tpd2 80% 20% OUT0~OUT257 -----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = H) 0.5 x VDD 0.5 x VDD 0.5 x VDD 0.5 x VDD ~ ~ 0.5 x VDD ~ ~ 0.5 x VDD CP tpd2 tpd2 tpd2 tpd2 tpd2 OUT0~257 80% 80% 20% 20% 80% VH VOFF VL tpd2 20% -----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = L) 0.5 x VDD 0.5 x VDD 0.5 x VDD 0.5 x VDD 0.5 x VDD CP tpd2 tpd2 tpd2 tpd2 VH tpd2 OUT0~OUT257 20% 80% 20% 80% VOFF 20% VL PRELIMINARY (August, 2001, Version 0.0) 10 AMIC Technology, Inc AD120 Timing Waveform (continued) XOFF 0.5 x V DD twOFF tpd3 tpd3 0.5 x V DD 80% 80% VOFF 20% OUT0~OUT257 20% VH VL ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ XON 0.5 x V DD 0.5 x V DD tpd4 tpd4 OUT0~OUT257 20% 80% VH PRELIMINARY (August, 2001, Version 0.0) 11 AMIC Technology, Inc AD120 Ordering Information Part No. AD120T Package TCP PRELIMINARY (August, 2001, Version 0.0) 12 AMIC Technology, Inc |
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